The invention relates to a circuit arrangement for calculating matrix operations which recur frequently, such as those in signal processing, especially in the context of neural networks. Since the computation operations which are required for calculating neural networks can be reduced to a comprehensible number of elementary matrix operations, it is sensible from the point of view of the necessary high computation speed in the execution of these operations to implement such computation operations in hardware, rather than to carry them out with the aid of software.
A prior art which is closest to the invention is reproduced in the publication by U. Ramacher, "Design of a first Generation Neurocomputer", VLSI Design of Neural Networks, edited by U. Ramacher, U. Ruckert, Kluwer Academic Publishers, Nov. 1990. This publication describes a circuit arrangement which is constructed from a systolic arrangement of multipliers and adders. This systolic arrangement makes it possible to calculate matrix products, the matrices which are to be multiplied being split into blocks of size 4.times.4, and it being possible to multiply submatrices of this size with the aid of the systolic arrangement in each case. The computation operations which can be carried out using this circuit arrangement are suitable for the calculation of specific neural network types, for example multilayer perceptron networks with feedback.
The disadvantages of this circuit arrangement, as it is described in the publication by U. Ramacher 1990, are primarily that:
the transposition, addition and subtraction are not supported by matrices,
result matrices cannot be squared or cannot be multiplied by a scalar, and that
the calculation of row and column sums and the search for extreme matrix elements are not supported by this circuit arrangement.
Furthermore, in the case of this circuit arrangement, there is no monitoring of the value range of the matrix coefficients, and the value ranges of the matrix elements are not limited if an overflow occurs.